1. Field of the Invention
The present invention relates to a semiconductor memory device. More particularly, the invention relates to a circuit and method for generating an internal power supply voltage in the semiconductor memory device.
2. Description of the Related Art
The power supply voltages used in a semiconductor memory device may be provided by an external power supply and/or an internal power supply.
Contemporary semiconductor memory devices intended for use in mobile host devices must be operated in a deep power-down (DPD) mode. While operating in DPD mode, semiconductor memory devices greatly reduce their power consumption. In one aspect, the DPD mode may be used when the external power supply voltage is provided and the internal power supply voltage is turned OFF. That is, when certain portions of the semiconductor memory device are deactivated, they may be placed in the DPD mode and the internal power supply voltage normally supplied to these portions may be turned OFF.
On the other hand, contemporary semiconductor memory devices also include a start mode of some kind. The start mode usually includes a power-up mode and/or a DPD exit mode. The power-up mode enables provision of a power supply voltage to the semiconductor memory device from a state in which both the external and internal power supply voltages are turned OFF. The DPD exit mode enables provision of a power supply voltage to the semiconductor memory device from a state in which the external power supply voltage is provided but the internal power supply voltage is turned OFF.
In a conventional method, the internal power supply voltage is generated from the external power supply voltage using an external initialization signal during the power-up mode. Thereafter, the internal power supply voltage is generated by an internal power supply voltage generator. In such a case, the transition time for generation of the internal power supply voltage is relatively short, and the hold time for an internal initialization signal is also relatively short. As a result, some internal circuits within the semiconductor memory device may not be completely reset during the DPD exit mode.